By Dimitris Gizopoulos
This is a brand new kind of edited quantity within the Frontiers in digital checking out booklet sequence dedicated to contemporary advances in digital circuits trying out. The e-book is a complete elaboration on vital issues which catch significant study and improvement efforts this present day. "Hot" issues of present curiosity to check know-how neighborhood were chosen, and the authors are key participants within the corresponding topics.
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Extra resources for Advances in Electronic Testing: Challenges and Methodologies
Slow functional At-speed functional 0 0 0 5 190 4 0 Stuck-at scan 8 0 22 6 2 24 At-speed (AC) scan Figure 1-27: Effectiveness of various test types . Three results are immediately clear: 1) at-speed tests are required to detect significant numbers of failing parts, 2) at-speed scan tests find most of the same failing parts as at-speed functional tests, plus some others, and 3) at-speed functional tests still find parts missed by other tests. 21 Pseudo-stuck-at fault coverage is calculated by applying a full stuck-at fault set within a standard cell, and requiring that these faults be propagated to the output of the cell.
Off 1 0 B on A off 0 1 Figure 1-23: Leakage induced faulty latch behavior. 5 DEFECT-ORIENTED TEST TYPES Now that we have looked at both defects and fault models, we are ready to apply them into a Defect-Oriented test strategy. This section describes the required elements of such a strategy; that is, a comprehensive approach to chip testing beginning with a defect analysis and comprising multiple test types or methods. 1 Logic Tests Logic testing, most typically using scan vectors, remains the most common and useful technique for quickly identifying bad parts.
16 Chapter 1 – Defect-Oriented Testing quality is always measured in terms of defects, while coverage can only be measured in terms of faults. But how do defects and faults relate to one another? It is sometimes desirable to use a simple model as a “surrogate” for a more complex model in order to quantify this relationship . Fault Diagnosis Fault models can be used as part of fault diagnosis and thus help find the root cause of defective chips. In its most basic form, algorithmic fault diagnosis consists of using a fault model to predict the behavior of faulty circuits, comparing these predictions to the actual observed behavior of defective chips, and identifying the predicted behavior(s) which most closely match the observations.